ASIC Design Engineer

【岗位职责】 1.ISP Module RTL Design：Design and implement RTL for one or more blocks in the ISP pipeline under the guidance of senior engineers or the module owner. 2.Micro-Architecture & PPA：Contribute to dataflow, line buffer and caching decisions; support PPA trade-offs across image quality, area, bandwidth and power. 3.Algorithm Mapping & Reference Model Alignment：Work with the algorithm team on fix…… 完整岗位描述与官方投递入口,请登录后在岗位详情页查看。